Patent Document 1 describes a semiconductor integrated circuit including a plurality of sense amplifiers. When the sense amplifiers are simultaneously driven and then peak current flows, power supply noise may be generated and a power supply voltage may be reduced. In order to prevent such a phenomenon, each of the sense amplifiers is driven at an independent timing in this semiconductor integrated circuit.
Patent Document 2 describes a flash memory including a plurality of memory cell arrays. In this flash memory, in addition to shifting timings of driving respective sense amplifiers, a precharge timing is also shifted for each memory cell array, thereby preventing precharge current concentration.
[Patent Document 1] JP Patent Kokai Publication No. JP-P2001-35167A
[Patent Document 2] WO2003/073430A1 Pamphlet